3rd NASA Symposium on VLSI Design
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3rd NASA Symposium on VLSI Design University of Idaho, Moscow, Idaho, October 30-31, 1991. by NASA Symposium on VLSI Design (3rd 1991 University of Idaho)

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Published by The University in [Moscow, Idaho .
Written in English


  • Integrated circuits -- Very large scale integration -- Design and construction -- Congresses.

Book details:

Edition Notes

Other titlesThird NASA Symposium on VLSI Design., Third NASA VLSI Design Symposium., NASA Symposium on VLSI Design.
ContributionsSpace Engineering Research Center (Tucson, Ariz.), United States. National Aeronautics and Space Administration. Data System Technology Working Group., Institute of Electrical and Electronics Engineers.
The Physical Object
Pagination1 v. (various pagings) :
ID Numbers
Open LibraryOL16903843M

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The 3rd NASA Symposium on VLSI Design Maki, Gary K. Abstract. Not Available. Publication: 3rd NASA Symposium on VLSI Design. Pub Date: The ADS is operated by the Smithsonian Astrophysical Observatory under NASA Cooperative Agreement Author: Gary K. Maki. 3rd NASA Symposium on VLSI Design N A Verification Logic Representation of Indeterministic Signal States;l. W. (]ambles and P. J. Windley NASA Space Engineering Research Center for VLSI Systems Design University of Idaho Moscow, Idaho Abstract - The integration of modern CAD tools with formal verification envi-. 3rd NASA Symposium on VLSI Design Once the network is trained, the number of connections is reduced. This is done by setting all weights having an absolute value less than a specified value to zero (no connect). This process is easily automated allowing various cut off values to be evaluated. The modified weight matrix is evaluated using. 3rd NASA Symposium on VLSI Design N Canonical Multi-Valued Input Reed-Muller Trees and Forms M. A. Perkowski 1 and P. D. Johnson Department of Electrical Engineering Portland State University P.O. Box , Portland, Oregon Abstract - There is recently an increased interest in logic synthesis using EXOR gates.

3rd NASA Symposium on VLSI Design then equation 3 can be rewritten as: Io t Vt_,_ (1 + fiT) (6) K2Rr_I (1 + a2T) When fl equals a_, Io_t has a zero temperature coefficient. The key to all this temperature coefficient cancellation is that all the components have . 3rd NASA Symposium on VLSI Design N An Improved Distributed Arithmetic Architecture X. Guo and D. W. Lynn NASA Space Engineering Research Center for VLSI System Design University of Idaho Moscow, Idaho AbJtract- Speed requirements have been, and will continue to be a major con-.   The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. A single phase dynamic CMOS NOR-NOR programmable logic array (PLA) using triggered decoders and charge sharing techniques for high speed and low power is presented. By using the triggered decoder technique, the ground switches are eliminated, thereby, making this new design much faster and lower power dissipation than conventional PLA's. By using the charge-sharing technique in a dynamic Author: Y. B. Dhong, C. P. Tsang.

Refereed Conference Publications and in Press N.K. Unnikrishnan and K.K. Parhi, "A Gradient-Interleaved Scheduler for Energy-Efficient Backpropagation for Training Neural Networks," Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS), Seville, Spain, May N.K. Unnikrishnan, M. Garrido, and K.K. Parhi, "Effect of Finite Word-Length on SQNR, Area and Power for Real-Valued. ADS Bibliographic Codes: Conference Proceedings Abbreviations vlsi symp 3rd NASA Symposium on VLSI Design wsa work 3rd NASA Workshop on Wiring for Space Applications paso conf 3rd National Passive Solar Conference nse book 3rd National Space Engineering Symposium csmy conf 3rd Paris Cosmology Colloquium. NASA Images Solar System Collection Ames Research Center. Brooklyn Museum. Full text of "VLSI Design" See other formats. In 3rd NASA Formal Methods Symposium, volume LNCS , pages , Pasadena, California, Sakallah, K. A.; and Rutenbar, R. A In Twelfth International Conference on VLSI Design, pages , Goa, India, In Proc. IFIP TC10 WG Tenth International Conference on Very Large Scale Integration (VLSI '99), pages , Lisbon.